1. Field of the Invention
The present invention generally relates to semiconductor devices and to insulating layers of semiconductor devices, and more particularly, the present invention relates to the formation of insulating layers, such as borophosphosilicate (BPSG) layers.
2. Description of the Related Art
Insulating and conductive layer fabricating techniques, utilized during manufacture of a semiconductor device, can largely be classified into two areas: physical vapor deposition and chemical vapor deposition. In the case of chemical vapor deposition (CVD), a gas source, that includes an element of an object material to be formed, and a reaction gas are supplied onto a substrate, and then the substrate is heated to initiate a chemical reaction to form a target layer on the substrate.
The CVD process characteristics used to form the layer affect not just the target layer, but also the previously formed underlying layer and any subsequent upper layers to be formed. Therefore, when forming the target layer, the chemical and physical characteristics should be sufficiently considered in view of both the process characteristics of the underlying layer and the upper layer to be formed.
A phosphosilicate glass (PSG) layer obtained by doping phosphorus into an oxide material, or a borophosphosilicate glass (BPSG) layer obtained by doping boron and phosphorus into an oxide material, are the primary layer types used as an insulating layer to protect a surface or to electrically isolate a conductive layer. This is mainly due to the excellent step coverage of these layers. Also, PSG and BPSG layers generate alkali ions while reacting as a diffusion wall against humidity, and the processes for forming the layers can be easily performed in a low temperature regime.
However, there is a disadvantage to using the PSG and BPSG layers. Since these layers exhibit fluidity and act as a diffusion wall during a reflow process, the layers also operate as an intermediary to transmit the humidity to the underlying layers. Accordingly, in a case where a layer is composed of a material that can be damaged by humidity, or where a substrate is made of silicon, the transfer of humidity may cause a serious problem. Therefore, a method to minimize the influence of the humidity has to be fully considered when the PSG or BPSG layers are being formed.
Examples of methods of forming PSG and BPSG insulating layers for minimizing the influence of the humidity are disclosed in U.S. Pat. No. 4,668,973 (issued to Dawson et al.), Japanese Patent Laid-Open No. Sho 59-222945, Japanese Patent Laid-Open No. Hei 1-122139 and Japanese Patent Laid-Open No. Hei 8-17926.
In U.S. Pat. No. 4,668,973, the PSG layer is formed by adding 7% or less of phosphorus on a silicon nitride layer after forming the silicon nitride layer on the substrate. Accordingly, the silicon nitride layer prevents the humidity from penetrating into the substrate even though the PSG layer has been reflowed. Furthermore, even if a window is formed at the PSG layer, the substrate may be prevented from being oxidized because the substrate is not directly exposed by means of the silicon nitride layer.
In Japanese Patent Laid-Open No. Sho 59-222945, a silicon nitride layer is formed on a substrate and then a BPSG layer is formed on the silicon nitride layer. The silicon nitride layer prevents the humidity from penetrating into the substrate even where the BPSG layer has been reflowed. Therefore, oxidation of the substrate by direct exposure is prevented.
In Japanese Patent Laid-Open No. Hei 1-122139, a silicon nitride layer is successively formed on the substrate and a gate electrode and thereafter a PSG layer containing boron is formed. The silicon nitride layer acts to prevent humidity from penetrating into the substrate or the gate electrode even where the PSG layer has been reflowed.
In Japanese Patent Laid-Open No. Hei 8-17926, a silicon oxide layer is formed onto a polysilicon layer and then the BPSG layer is formed onto the silicon oxide layer. Therefore, the silicon oxide layer prevents the humidity from penetrating into the polysilicon layer or the substrate even if the BPSG layer has been reflowed.
In this way, when the PSG layer or BPSG layer is formed, the effect of the humidity can be minimized by means of forming the PSG layer or BPSG layer on the underlying silicon nitride layer. Also, the silicon nitride layer prevents the underlying layer or the substrate from being damaged by means of etching, for example, when a portion of the insulating layer is patterned and etched to form a window.
When fabricating semiconductor devices having elevated regions and recessed regions composed of minute windows or gate electrodes, one must consider the need to sufficiently flow and/or fill the BPSG insulating layer into and/or up the recessed regions of the windows or the gate electrodes. Therefore, a chemical vapor deposition using a tetraethylorthosilicate (TEOS), a triethylborate (TEB), a triethylphosphate (TEPO), an oxygen gas, and an ozone gas is employed to form the BPSG layer.
As described above, first the silicon nitride layer is formed and then the BPSG layer is formed, in order to prevent the damage due to the penetration of the humidity and the etching and to obtain a sufficient filling characteristic.
The BPSG layer is formed as follows. First, an oxidizing atmosphere for easily forming the BPSG layer is prepared using an oxygen gas. After forming a first seed layer onto a silicon nitride etch stop layer using TEOS and oxygen gas, a second seed layer is formed onto the first seed layer using TEB, TEPO, TEOS and oxygen gas. The constituents of the first and second seed layers determine the amount of boron and phosphorus added into the BPSG layer. Subsequently, the BPSG layer is formed onto the etch stop layer including the first and the second seed layers by using TEB, TEPO, TEOS and ozone gas. At this time, the BPSG layer is formed with a relatively large amount of phosphorus because TEPO is used to form the second seed layer.
The BPSG layer is then reflowed utilizing nitrogen gas to planarize the surface of the BPSG layer, as well as attempt to sufficiently fill the recessed regions with this BPSG insulating layer among the elevated regions and recessed regions.
However, if the BPSG layer does not have sufficient fluidity during this reflow process with nitrogen, the BPSG layer will not sufficiently flow and/or fill into and/or up the recessed regions of the windows or the gate electrodes, and accordingly, voids are generated. Therefore, an oxygen gas and a hydrogen gas are sometimes used instead of the nitrogen gas to reflow the BPSG layer to minimize the generation of the voids.
However, when the BPSG layer has been reflowed with the oxygen gas and the hydrogen gas, the thickness of the etch stop layer under the BPSG layer is decreased. This is because phosphoric acid H3PO4 is generated by a chemical reaction between the triethylphosphate (TEPO), which determines the amount of phosphorus in the layer, and the oxygen gas and the hydrogen gas, and the phosphoric acid etches the etch stop layer while the reflowing is being performed.
Based on a transmission electron microscope (TEM) analysis of the etch stop layer before and after the reflow process, it was found that the thickness of the etch stop layer decreased by about 30% after reflowing the BPSG layer using oxygen and hydrogen gases. Also, based on an auger electron spectroscopy (AES) analysis, it was found that the oxidized materials composing the etch stop layer after reflowing were increased about 0.2 times more than before reflowing. Thus, it is confirmed that the thickness of the etch stop layer is decreased by the reflowing process and the oxidization progresses thereby.
Accordingly, the etch stop layer is unable to appropriately control the etching process when the BPSG layer is etched to form a BPSG layer pattern having a window after the reflowing. Consequently, the substrate under the etch stop layer is exposed, or even the substrate itself is etched. In a semiconductor device fabricating process which requires a fine pattern such as a self-aligned contact, the decrease in thickness of the etch stop layer precludes attaining a sufficient shoulder margin between the gate electrodes.
In contrast, even when using a BPSG layer containing a relatively large amount of boron, rather than the PSG layer containing a relatively large amount of phosphorus, the BPSG layer is not filled into the recessed regions and voids are created because the BPSG layer does not have sufficient fluidity. Also, since the BPSG layer has an isotropic etch characteristic, the etched window that is formed is larger than a predetermined critical dimension CD. Therefore, in the subsequent process for filling up the window, the window is not sufficiently filled up and a void is generated. This is because the window is formed to have a size larger than the predetermined CD, however, the filling of the window is implemented with the CD as a reference.
As described above, since the amount of phosphorus and boron added to the BPSG layer is not controlled, the thickness of the underlying etch stop layer decreases, or the etch stop layer has the isotropic etch characteristic, whereby the reliability of the semiconductor device fabricating method is reduced.
A patent application describing a method of manufacturing a BPSG layer, having substantially no characteristic change by precisely controlling the amount of phosphorus and boron, was filed in the U.S. Patent Office by certain of the present inventors (and having a common assignee) on Mar. 8, 2001 as Ser. No. 09/800,892, and entitled xe2x80x9cINSULATING LAYER, SEMICONDUCTOR DEVICE AND METHODS FOR FABRICATING THE SAMExe2x80x9d.
According to the method disclosed in the ""892 patent application, even though the BPSG layer is reflowed by utilizing a hydrogen gas and an oxygen gas, the decrease of the thickness of an etch stop layer is minimized and a sufficient filling effect and anisotropic etch characteristic can be accomplished by appropriately controlling the amount of phosphorus and boron in the BPSG layer.
FIG. 1 is a graph illustrating experimental BPSG layers having common elements manufactured by like, but discrete, apparatuses. Except for one instance, the thickness decreases of the etch stop layers range from about 35 xc3x85 to about 45 xc3x85, after implementing the reflowing of the BPSG layer. Efforts are now being expended to further increase the reproducibility of the decrease of the thickness of the etch stop layer across like, but discrete, apparatuses for implementing the chemical vapor deposition process.
In light of the above, it is therefore an object of the present invention to provide a method of manufacturing an insulating layer having substantially the same characteristics, regardless of the particular apparatus used to manufacture the insulating layer.
Another object of the present invention is to provide a semiconductor device and a method of manufacturing the semiconductor device including an insulating layer having substantially the same characteristics that affect an underlying layer, regardless of the particular apparatus used to manufacture the insulating layer.
To accomplish these and other objects, the present invention provides a method of manufacturing an insulating layer including first creating a process atmosphere in a chamber and then forming a fluidal insulating layer on a substrate within the chamber.
The process atmosphere is created by (a) flowing an oxidizing gas at an oxidizing gas flow rate for forming an oxidizing atmosphere, (b) flowing a first carrier gas at a first carrier gas flow rate, and (c) flowing a second carrier gas at a second carrier gas flow rate, the second carrier gas flow rate being greater than the first carrier gas flow rate.
The fluidal insulating layer is formed on the substrate positioned in the chamber by (d) flowing the oxidizing gas at the oxidizing gas flow rate, (e) flowing the first carrier gas at the first carrier gas flow rate while carrying a first impurity including boron flowing at a first impurity flow rate, (f) flowing the second carrier gas at the second carrier gas flow rate while carrying a second impurity including phosphorus flowing at a second impurity flow rate, the second carrier gas flow rate being greater than the first carrier gas flow rate, and (g) flowing a silicon source material at a silicon source flow rate.
The oxidizing gas is one selected from a group consisting of oxygen gas, ozone gas and a mixture thereof, the first carrier gas is a nitrogen gas, the second carrier gas is a helium gas, the silicon source material is tetraethylorthosilicate (TEOS), the first impurity is one selected from a group consisting of triethylborate (TEB), trimethylborate (TMB), and a mixture thereof, and the second impurity is one selected from a group consisting of triethylphosphate (TEPO), trimethylphosphate (TMPO) and a mixture thereof.
For the process atmosphere, the ratio of the oxidizing gas flow rate, the first carrier gas flow rate, and the second carrier gas flow rate is about 1.00-2.50:0.70-0.95:1, and preferably the second carrier gas flow rate is at least 4,000 sccm.
For the fluidal insulating layer, the ratio of the oxidizing gas flow rate, the first carrier gas flow rate, the second carrier gas flow rate, the silicon source flow rate, the first impurity flow rate, and the second impurity flow rate is about 2.00-2.50:0.70-0.95:1:0.15-0.25:0.040-0.045:0.013-0.014, and preferably the second carrier gas flow rate is at least 4,000 sccm. The fluidal insulating layer may be reflowed after the forming thereof.
An etch stop layer may be formed on the substrate prior to forming the fluidal insulating layer, and an undoped fluidal insulating layer may be interposed between the etch stop layer and the fluidal insulating layer.
For the undoped fluidal insulating layer, a ratio of the oxidizing gas flow rate, the first carrier gas flow rate, the second carrier gas flow rate, and the silicon source flow rate is about 2.00-2.50:0.70-0.95:1:0.15-0.25, and preferably the second carrier gas flow rate is at least 4,000 sccm.
In another aspect, the present invention provides a semiconductor device including a substrate having a gate electrode formed at an upper portion of the substrate, and a source and a drain formed at a lower portion of both sides of the gate electrode.
An insulating layer is continuously formed on the substrate and the gate electrode, the insulating layer being formed by (a) flowing the oxidizing gas at the oxidizing gas flow rate, (b) flowing the first carrier gas at the first carrier gas flow rate while carrying a first impurity including boron flowing at a first impurity flow rate, (c) flowing the second carrier gas at the second carrier gas flow rate while carrying a second impurity including phosphorus flowing at a second impurity flow rate, and (d) flowing a silicon source material at a silicon source flow rate.
For the insulating layer composition, a ratio of the oxidizing gas flow rate, the first carrier gas flow rate, the second carrier gas flow rate, the silicon source flow rate, the first impurity flow rate, and the second impurity flow rate is about 2.00-2.50:0.70-0.95:1:0.15-0.25:0.040-0.045:0.013-0.014, and wherein a flow rate of the second carrier gas is preferably at least 4,000 sccm.
The oxidizing gas is one selected from a group consisting of oxygen gas, ozone gas and a mixture thereof, the first carrier gas is a nitrogen gas, the second carrier gas is a helium gas, the silicon source material is tetraethylorthosilicate (TEOS), the first impurity is one selected from a group consisting of triethylborate (TEB), trimethylborate (TMB), and a mixture thereof, and the second impurity is one selected from a group consisting of triethylphosphate (TEPO), trimethylphosphate (TMPO) and a mixture thereof.
The semiconductor device may also have an etch stop layer formed on the substrate and which underlies the insulating layer. In addition, the semiconductor device may further include an undoped insulating layer interposed between the etch stop layer and the insulating layer.
For the undoped insulating layer composition, the ratio of the oxidizing gas flow rate, the first carrier gas flow rate, the second carrier gas flow rate, and the silicon source flow rate is about 2.00-2.50:0.70-0.95:1:0.15-0.25.
According to the present invention, the characteristics of the insulating layer can be reproduced with great certainty, across a plurality of like apparatuses. Moreover, the insulating layer can be employed when implementing a self aligned contact process and when forming a fine pattern with a design rule of 0.15 xcexcm or less.